In recent years, various kinds of integrated circuit chips have been developed in which a memory is incorporated in a logic section such as ASIC or microprocessor. As the integrated circuit chips become more and more complex, test apparatus for properly and extensively testing the chips accordingly increases in number and complexity. In order to reduce the complexity and reliance upon external test apparatus, on-chip test circuits are provided in the integrated circuits for autonomously conducting at least part of the test. The circuit is commonly referred to as built-in self test (BIST) circuit.
The BIST circuit is a technique of designing additional hardware and software features into the integrated circuits to allow them to perform self-testing using their own circuits. The BIST circuit used in memory devices such as EPROMs, EEPROMs, SRAMs, DRAMs, flash memories, or microprocessors or microcontrollers with embedded RAMs and ROMs, typically consists of test circuits that apply, read, and compare test patterns designed to expose potential physical failures in the memory device. Specifically, the BIST circuit may generate a characteristic signature related with data stored in the memory according to a certain algorithm, for example, a cyclic redundancy check (CRC) algorithm. Further, the BIST circuit may compare the characteristic signature with a test signature obtained during the BIST test process. If a difference between the characteristic signature and the test signature occurs, the memory device is considered as a failed device.
However, the BIST test process is generally transparent to test engineers. Only a few test information can be provided by the BIST circuit, and therefore it is difficult for test engineers or fabrication engineers to analyze the root cause for the physical failures.
Thus, there is a need for a failure diagnosis circuit for integrated circuits with more flexibility and low cost.